(1) Field of the Invention
This invention relates generally to transistor drivers and relates more specifically to a driver for a high voltage P-MOS power transistor having accurate control voltage and faster switching.
(2) Description of the Prior Art
For applications as e.g. automotive applications supply voltages up to 40 Volts and even higher are often required. High-Voltage CMOS devices are usually based on a 5V technology with an extended drain region to reach up to e.g. 40V drain-source breakdown capability. As the source side of the High-Voltage CMOS devices is the same as it is for 5-V CMOS devices, its bulk-source voltage, Vbs, as well as its gate-source voltage, Vgs, are limited to 5V. Static power dissipation of the high voltage (HV) transistors, achieving accurate control voltage of e.g. 5 Volts and high switching speed are key problems with high voltage CMOS devices, which should be overcome.
It is a challenge for engineers designing driver circuits for high voltage applications, i.e. supply voltages in the order of magnitude of 40 V to overcome above problems.
(U.S. Pat. No. 6,507,226 to Swonger et al.) discloses a circuit and method translating a logic level input signal to signals at high voltage levels to drive a power device, such as a power MOSFET, while minimizing the power consumption. The circuit for driving the power device includes a low side gate driver, and a high side gate driver adjacent thereto. The high side gate drive includes a high side gate driver logic input, a high side gate driver output, a latch connected between the high side gate driver logic input and the high side gate driver output, and a control circuit receiving an output of the latch and controlling signals from the high side gate driver logic input to the latch based upon the output of the latch.
(U.S. Pat. No. 5,325,258 to Choi et al.) discloses a circuit and method for driving a power transistor device. The circuit for driving a power transistor device has a driver having an input and an output, the output coupled to a control input of the power transistor device and the input coupled to a primary control voltage source for driving the power transistor device. A current sensing device is coupled to the power transistor device for providing a signal proportional to the current in the power transistor device. An amplifier is coupled to the current sensing device for providing a substantially linear control signal proportional to the current in the power transistor device, the linear control signal being provided to the input of the driver as a secondary drive signal for driving the power transistor device when a current level in the power transistor device greater than a threshold level is detected. A detector is provided for detecting when the current in the power transistor device is greater than the threshold level. The detector is coupled to the current sensing device and to a reference level source, and provides an overcurrent signal to the driver for switching the driver from being driven by the primary control voltage source to the secondary drive signal. The secondary drive signal drives the driver so as to reduce the current level in the power transistor device. The driven power transistor device is preferably a power MOSFET or IGBT.
(U.S. Pat. No. 4,937,477 to Tsoi et al.) proposes a high-voltage level translator circuit that is suitable for monolithic integration. The level translator circuit comprises serially connected current sources suitably ratioed so that the gating on of one current source causes a limited voltage rise across the other current source, which is ungated. The circuit is suitable for integration in a junction-isolated monolithic pseudo-complementary CMOS format.